VHDL Programming

(C. Jardin) #1

68 Chapter Three


This statement inside of a process statement schedules an event for
signal selon the next delta time point, with the value 0. However, pro-
cessing continues in the process statement with the next sequential state-
ment. The value of selremains at whatever value it had at the entry to
the process. Only when the process has completed is this current delta
finished and the next delta time point started. Only then is the new value
of selreflected. By this time, however, the rest of the process has already
been processed using the wrong value of sel.
There are two ways to fix this problem. The first is to insert WAITstate-
ments after each sequential signal assignment statement as shown here:

ARCHITECTURE mux_fix1 OF mux IS
SIGNAL sel : INTEGER RANGE 0 TO 3;
BEGIN
PROCESS
BEGIN
sel <= 0;
WAIT FOR 0 ns; -- or wait on sel

IF (a = ‘ 1 ’) THEN sel <= sel + 1; END IF;
WAIT for 0 ns;

IF (b = ‘ 1 ’) THEN sel <= sel + 2; END IF;
WAIT FOR 0 ns;

CASE sel IS
WHEN 0 =>
Q <= I0;
WHEN 1 =>
Q <= I1;
WHEN 2 =>
Q <= I2;
WHEN 3 =>
Q <= I3;
END CASE;

WAIT ON A, B, I0, I1, I2, I3;
END PROCESS;
END mux_fix1;

The WAITstatements after each signal assignment cause the process to
wait for one delta time point before continuing with the execution. By
waiting for one delta time point, the new value has a chance to propagate.
Therefore, when execution continues after the WAITstatement, signal sel
has the new value.
One consequence of the WAITstatements, however, is that the process can
no longer have a sensitivity list. A process with WAITstatements contained
within it or within a subprogram called from within the process cannot
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