72 Chapter Three
that is sensitive to the signal in its expression. For instance, the first as-
sertion is sensitive to signal Abecause that signal is contained in its ex-
pression.SUMMARY
In this chapter, we discussed the following:How process statements are concurrent statements that delineate
areas of sequential statements.How process statements can be used to control when a process is
activated.How signal assignments are scheduled and variable assignments
happen immediately within a process statement.How IF,CASE, and LOOPstatements can be used to control the flow
of execution within a model.How ASSERTIONstatements can be used to check for error condi-
tions or report information to the user.The three forms of the WAITstatement. How WAIT UNTILis used
for specifying clocks for synthesis, and how WAIT ONcan be used to
modify the sensitivity list.How passive processes can be used to perform error checking and
other tasks across a number of architectures by existing in an
ENTITYstatement.The next chapter focuses on all of the different data types of VHDL that
can be used in models.