VHDL Programming

76 Chapter Four

for board_design. The signal sys_clkcan therefore be assigned to and

read from in entity board_designand architecture data_flow.

ARCHITECTURE LOCAL SIGNALS Inside of architecture

data_flowis a signal declaration for signal int_bus. Signal int_busis of

type bus_type, a type defined in package sigdecl. The sigdeclpackage is

used in entity board; therefore, the type bus_typeis available in architec-

ture data_flow. Because the signal is declared in the architecture decla-

ration section, the signal can only be referenced in architecture data_flow

or in any process statements in the architecture.

Variables

Variables are used for local storage in process statements and subprograms.

(Subprograms are discussed in Chapter 6,“Predefined Attributes.”) As

opposed to signals, which have their values scheduled in the future, all

assignments to variables occur immediately. A variable declaration looks

like this:

VARIABLE variable_name {,variable_name} : variable_type[:=

value];

The keyword VARIABLEis followed by one or more variable names. Each

name creates a new variable. The construct variable_typedefines the

data type of the variable, and an optional initial value can be specified.

Variables can be declared in the process declaration and subprogram

declaration sections only. An example using two variables is shown here:

LIBRARY IEEE;

USE IEEE.std_logic_1164.ALL;

ENTITY and5 IS

PORT ( a, b, c, d, e : IN std_logic;

PORT ( q : OUT std_logic);

END and5;

ARCHITECTURE and5 OF and5 IS

BEGIN

PROCESS(a, b, c, d, e)

VARIABLE state : std_logic;

VARIABLE delay : time;

BEGIN

state := a AND b AND c AND d AND e;

IF state = ‘ 1 ’ THEN