Microsoft Word - Digital Logic Design v_4_6a

 The state diagram showing the effect of Latch Control (C) on the state change.

Note: This circuit, like the SR Latch Circuit, has a critical race when CSR transitions from

111 to CSR=100. To prevent this issue, it is possible not to allow CSR=111.

Q=0 Q=1

Hold 0

C S R

1 0 0

1 0 1

1 1 1

0 0 0

0 0 1

0 1 0

0 1 0

Reset

C S R

1 1 1

1 0 1

Hold 1

C S R

1 0 0

1 1 0

0 0 0

0 0 1

0 1 0

Set 0 1 0^

C S R

1 1 0

When C=0, there is no state change

Q=0 Q=1

C.S.R’

C’ + S’ +R

C.R

C’+R’

* Another form of State Diagram for the same circuit is shown below: