So you can use this design to implement a positive-edge-triggered D flip-flop circuit with
preset and clear inputs.
∆t
(delay)
Q’
Q Q
+
C
D
(Clear)’
(PreSet)’
Circuit Diagram
X
Y Z^
X
Y
Z
tp tp
A pulse is generated only during the rising edge
So you can use this design to implement a positive-edge-triggered D flip-flop circuit with
preset and clear inputs.
∆t
(delay)
(Clear)’
(PreSet)’
Circuit Diagram
tp tp
A pulse is generated only during the rising edge