Microsoft Word - Digital Logic Design v_4_6a

Y 1 + =

Y 2 + =

4) Obtain a PS/NS table.

5) Use the PS/NS table or the composite K-map to obtain a state diagram to show the behavior

of the circuit.

 Input Date Synchronization
Synchronized systems have to accept external-inputs that may not be synchronized with the system
clock. Typically, an input is synchronized with the rising or falling edge of the system clock prior to
using it in the system:

 In-Phase Synchronization is when the input is synchronized with the rising edge of the system

clock.


 Anti-Phase Synchronization is when the input is synchronized with the falling edge of the system

clock.

Rising

Edge

Falling

Edge

Y 1 Y 2 X Y 1 + Y 2 + Z

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

PS/NS Table