Microsoft Word - Digital Logic Design v_4_6a

5.2. Synchronous Finite State Machine Design (Classical Design)

 Common Examples of Synchronous FSM

Up and Down Binary Counters

Shift Registers

Sequence Detectors

Controllers

 The Seven-Step Design Process for Synchronous Sequential Design (Classical Design)

1) Organizing the Design Specifications –Use one or more of the following tools:

System Diagram, Timing Diagram, State Diagram or ASM Chart.

2) Determine the number of flip-flops based on the number of states

At this point, designer may choose to design a full encoding or one-hot encoding. Full

encoding utilize all possible combinations of the flip-flops and the following inequality is used

to decide the number of flip-flops:

2 #flip-flop ≥ # States

The other encoding option is one-hot encoding where state is defined by which flip-flop’s

output is 1. So the number of flip-flop is equal to the number of States.

Once the number of flip-flops is determined, assign one variable for each of the flip-flop

output.

3) Assign a unique code to each state (a specific value for present state variables)

4) Select the flip-flop type to be used, draw the Present State/Next State (PS/NS) table,

determine the excitation input equations and the Moore and/or Mealy output equations.

Remember the excitation input and next state relationship flip-flops:

or Y J Y KY

K Y

J Y

JK Flip Flop

TFlip Flop T Y Y or Y T Y

DFlip Flop D Y or Y D

= .. +.

=

=

⇒

⇒ = ⊕ = ⊕

⇒ = =

+

+

+

+ +

+ +

Note: D flip-flops are generally preferred for most synchronous sequential designs.

5) Draw the circuit schematic (paper or CAD tool).

6) Perform a simulation to test the functionally of the design.

7) Implement the design with hardware.