Step 5) Draw the Circuit Schematic.
Steps 6 & 7) Testing and hardware implementation will be skipped for this example.
A Second Application of the Classical Design Process:
Design a synchronous sequential circuit called “Div-by-3”, having an output Z that divides the system
clock frequency fCLK by 3. The output duty cycle of two-thirds (2 CLK cycle high, 1 cycle low). Design
the circuit using positive-edge-triggered flip-flops.
Step1) Design Specifications Using a Timing Diagram
Step 2) Determine the number of flip-flop based on the number of State
(# state = 3) ≤ 2 (#flip-flop = 2) Assuming Full Coding
Step 3) Assign a unique code to each state
a: 00, b:01; C:11
Step 4) Write the excitation-input equations
The D flip flop excitation equation is D = Y +
CLK
CLR’
Z (output)
Y1(msb)
a
ST = Tclk
b
ST = Tclk
c
ST = Tclk
a
ST = Tclk
b
ST = Tclk
Timing Events 1 2 3 4 5 6 7
b
ST = Tclk
1 T clk’
2 T clk’