Microsoft Word - Digital Logic Design v_4_6a

 Draw the composite K-map for each of the desired outputs Y1+ ,Y2 +, Z:

Step 5) Draw the Circuit Schematic

Another Application of the Classical Design Process (using JK flip-flops)
Design a synchronous sequential circuit identical to the previous example, except implement the
design using JK flip-flops.

Step1) Design Specifications Using a Timing Diagram

CLK

CLR’

Z (output)

Y1(msb)

a

ST = Tclk

b

ST = Tclk

c

ST = Tclk

a

ST = Tclk

b

ST = Tclk

Timing Events 1 2 3 4 5 6 7

c

ST = Tclk

1 T clk’

2 T clk’

Y2

T1

Q1

CLK

Q1’

R1

T2

Q2

CLK

Q2’

R2

CLR’

SYS CLK

Y1

Y2

Y2’

T1

T2

Z

Y1’

00

01

11

10

T1 = Y2

T2 = Y1’ Y2’ + Y1Y2 = Y1 XNOR Y2

Z= Y1’

Note: “-“ means don’t care

Y1Y2 T1 T2 Z

0 1 1

1 0 1

1 1 0

- - -