Step 5) Draw the Circuit Schematic
Step 6) Test (with a test plan)
Step 7) Implement
Determining the Maximum Clock Frequency of a Synchronous State Machine
The maximum clock frequency that a system can handle is driven by the set-up, hold and margin
times required by the flip flops in the synchronous system.
We can see that the clock frequency is limited by fmax =1/TCLK(min) as shown below:
TCLK(min) = tpff(max) + tpcomb(max) + tmarg) + tsu + th where
tpff(max) = Maximum propagation delay time through flip-flop from the clock tick to Q output
tcomb(max) = Maximum propagation delay time through combinational logic
tmarg) = Margin time, it is always a good design practice to allow for tolerances.
tsu = Set-up time requirement
th = Hold time requirement
Note: We assume that th + th(marg) < tpff(min) + tpcomb(min)
EXAMPLE - Timing
Determine the absolute maximum clock frequency for the divide-by-3 synchronous machine
CLK
TCLK (^) (min)
tpff (^) (max)
Tpff (^) (min)
tpcomb (^) (max) Tpcomb^ (min)
tsu (^) (marg) tsu th th(marg)
INPUT
OUTPUT