Microsoft Word - Digital Logic Design v_4_6a

5.6. FSM Design Examples

 Design a 3-bit up/down binary counter.

Solution:

Step 1 – State Diagram Describing the system

Step 2 - 8 possible state  3 Flip Flops required

Use D flip flop since not specified.

Step 3 – Assign State variables and redraw state diagram

Zero One^

Seven (^) Six
Note:
Counter changes with each clock which is not shown on state diagram.
up
up
up
Two
up
Down
up
Down
Three
four
down up^
down
Down
down
five
down
up
down
up

UD

0 – up

1 - down

Up/Down

3-bit Binary

Counter

c 0

c 1

c 2

count 0-7