Microsoft Word - Digital Logic Design v_4_6a

If modify the above code by adding a sensitivity list which includes Bin and a clk. now the always
block will only be executed when Bin or clk change.

It is important to remember that always block cannot make an assignment to a wire but can drive
reg and integer data typed.

If we go back to the d-ff example, you see that always can be triggered on specific type of

module example(Ain, Bin, clk, Cout);

input Ain, Bin, clk;

wire Ain, Bin, clk;

output Cout;

reg Cout;

integer i, count;

initial // set the initial value of variables.

begin

i = 0;

count =0;

Ain =0;

Bin =0;

end //initial

always @ (Bin, clk) //Executes only when clk or bin change

begin

Cout = Ain; // Cout is equal to Ain only if clk or Bin have changed.

end

endmodule // end of module

module example(Ain, Bin, Cout);

input Ain, Bin;

wire Ain, Bin;

output Cout;

reg Cout;

integer i, count;

initial // set the initial value of variables.

begin

i = 0;

count =0;

Ain =0;

Bin =0;

end //initial

always

begin

# 5 Cout = Ain; // Cout becomes equal to Ain after delay of 5 time unit

end

endmodule // end of module