7.8. Flow Control Statements
Verilog much like C programming languages provides a wide variety of flow control statement. This
section will cover some of the most common flow control statements including “if-else”, “case’, “for”, and
“while”. Even though the functionality and syntax are similar C programming language
Even though the functionality appears to be the same as C, Verilog is an Hardware description language
so the codes has to translate to hardware. Meaning, that from time-to-time, special care needs to be
taken to ensure that design is implementation in hardware.
If-else Statement
if-else statement will execute the “T statements” if the conditions are true and execute the “F
statements” otherwise. The syntax is shown below:
Example - Case Statement
Case statement is preferred approach instead of complex nested if-else statements. Case statements
allows selection of a specific set of statements to be executed based on the specific values of a
selection variable.
Example -case (caseExp) // Select Variable
exp1 : statements 1 ; // if caseExp = exp1 then statement1 will be executed
exp2 : statements 2; // if caseExp = exp2 then statement2 will be executed
exp3 : statements 3; // if caseExp = exp3 then statement3 will be executed
default : statements; // if none of value matched then this statement is executed
endcase// simple if-else statement
if (test == 1’b1)
begin
count = 2;
wr_data = 16’hAE;
end
else
begin
count = count - 1;
wr_data = 0;
endif (condition) // condition is a logincal operation resulting in true or false
begin
T Statements // if condition is true, execute T Statements
end
else
begin
F Statements // if condition is true, execute F Statements
end