General VHDL Semantics
VHDL similar to other languages has many constructs and rules. The following list contain some of
the most common Semantics:
Code can span multiple lines and files for larger designs.
Comment field starts with “--" and ends at the end of line.
Each statement must be terminated with a “;”.
VHDL ignores space and line breaks which allows for readability formatting.
VHDL has many reserved words (or keywords) that cannot be redefined such as:
Entity, Port, Is, In, Out, End, Architecture, Begin, When, Else, Not, ...
Reserve words and identifiers are not case-sensitive
User Defined Identifiers
These are names used to refer to variables, signals, types, processes, function, types,
architecture and entities. User defined identifiers names must adhere to the following
requirements:
Must begin with a letter and contain letters, digits and underscores.
Underscore cannot follow each other and cannot be the first or last character.
Reserve words are not allowed.
Architecture A
Entity A
Architecture B
Entity B
Architecture C
Entity C
Architecture D
Entity D
Architecture E
Entity E
Architecture F
Entity F