8.8. Dataflow Design Elements............................................................................................................
A behavioral design relies on VHDL’s dataflow elements in describing the desired behavior. The
remainder of this section is focused on the most commonly used dataflow elements.
Concurrent “when signal” assignments
Syntax
signal_name <= expression; -- Concurrent signal assignment statement
signal_name <= expression when boolean_expression else -- conditional concurrent
expression when boolean_expression else -- signal assignment statements...
expression when boolean_expression else
expression ;
Example— Use the Dataflow elements to write the architecture for the prime number detector
(behavioral design).architecture prime2_arch of prime is
signal N3L_N0, N3_N2L_N1, N2L_N1_N0, N2_N1L_N0: STD_LOGIC;
begin
N3L_N0 <= 1 when (not N(3) and N(0)) else 0 ;
N3L_N2L_N1 <= 1 when (not N(3) and not N(2) and N(1)) else 0;
N2L_N1_N0 <= 1 when (not N(2) and N(1) and N(0)) else 0;
N2_N1L_N0 <= 1 when (N(2) and not N(1) and N(0)) else 0;
F <= 1 when (N3L_N0 or N3L_N2L_N1 or N2L_N1_N0 or N2_N1L_N0) ;
end prime2_arch;The prime number detector can also be implemented using conditional concurrent assignment
statements. Concurrent “selected signal” assignment
This statement evaluates the given expression when it matches one of the choices, then it assigns
the corresponding signal_value to signal_name.
Syntaxwith expression select
Signal_name <= signal_value when choices,
signal_value when choices,...
signal_value when choices,
signal_value when others;
The choices for the entire statement must be mutually exclusive.
The statement with keyword others will be used when none of the other choices matches the
expression results.
Choices may be a single value of expression of a list of values, separated by vertical bars “|”. Example – Implement a prime number detector using selected signal assignment.architecture prime3_arch of prime is
begin
with N select