0195136047.pdf

6.1 DIGITAL BUILDING BLOCKS 291

instruction should not be used. Figure 6.1.17(b) summarizes the specification for an SRFF

in terms of a truth table, in whichQnis the state of the circuit before a clock pulse and

Qn+ 1 is the state of the circuit following a clock pulse.

EXAMPLE 6.1.13

The inputs to an SRFF are shown in Figure E6.1.13. Determine the value ofQat timest 1 ,t 2 ,
andt 3.

S

R

0

1

1

0

t 0 t 1 t 2 t 3

Figure E6.1.13

Solution

Notice that the value ofQat timet 0 is not given; however, it is not necessary to have this
information. The first pulse ofSsets the SRFF in the stateQ=1. Thus att=t 1 ,Q=1. While
the second pulse ofStries again to set the SRFF, there will be no change sinceQwas already 1.
Thus att=t 2 ,Q=1. The pulse ofRthen resets the SRFF and then att=t 3 ,Q=0.

Flip-flops can be constructed using combinations of logic blocks. Therealizationof an SRFF
can be achieved from two NAND gates (plus two inverters), as shown in Figure 6.1.18. Because
of the feedback in this circuit it is not possible to simply write its truth table, as we can do for a
combinational circuit. However, a modified truth-table method can be used, in which we guess

SQ

RQ

SR

00

01

10

11

Qn+ 1 Qn+ 1

Qn Qn

01

10

Not allowed

(a) (b)

Inputs

Normal

Complementary

Outputs

SET

RESET

Inputs

Outputs

Figure 6.1.17SR flip-flop (SRFF)(a)Symbol.(b)Truth table.

Q

Q

S

R

Figure 6.1.18Realization of SRFF from two

NAND gates.