0195136047.pdf

PROBLEMS 331

x

y

z

f

Figure P6.1.28

z

y

x

f

Figure P6.1.29

xyzf

0001

0010

0101

0110

1001

1010

1100

1110

6.1.32With the use of a K map, simplify the following
Boolean expressions and draw the logic diagram.

(a) F 1 =A·B+B ̄·C+A·B·D+A·C·D

(b) F 2 =(X+Y)·(X ̄+Z)·(Y+Z) ̄

(c) F 3 =A·C+B·C ̄+A·B·C

(d) F 4 =(X ̄+Y)·(X+Z) ̄ ·(Y+Z)

6.1.33The K map of a logic function is shown in Figure
P6.1.33.
(a) Obtain a POS expression and its correspond-
ing realization.
(b) For the purpose of comparison, obtain the
corresponding SOP circuit, and comment on
the number of gates needed.

*6.1.34Given the K map of a logic function as shown

in Figure P6.1.34, in whichds denote don’t-care

conditions, obtain the SOP expression.

6.1.35The K map of a logic function is shown in Figure

P6.1.35, in whichds denote don’t-care conditions.

Obtain the SOP expressions.

6.1.36Obtain a minimum two-level NAND–NAND

realization for the following Boolean expressions.

(a)F(A,B,C)=

∑

mi( 1 , 6 )+

∑

di( 2 , 4 , 5 )

(b)F(A,B,C,D)=

∑

∑ mi(^0 ,^4 ,^5 ,^7 ,^13 )+

di( 2 , 6 , 8 , 10 , 11 )

Note that

∑

di()denotes the sum of minterms

corresponding to don’t-care outputs.

6.1.37(a) Show the equivalent NOR realizations of the

basic NOT, OR, and AND gates.

(b) Show the equivalent NAND realization of the

basic NOT, AND, and OR gates.

6.1.38Using a minimum number of NAND gates, realize

the following Boolean expression:∑ F(A,B,C)=

mi( 0 , 3 , 4 , 5 , 7 ).

6.1.39Figure P6.1.39 shows afull adderwith the idea of

addingCito the partial sumS′, which is the same

logic process as addition with pencil and paper.

(a) Draw the truth table for the full adder.

(b) Add decimal numbersA=7 andB=3in

binary form, showing the values ofA, B, S′,

AB

00

01

11

10

00 01 11 10

0000

0000

0001

0100

CD

Figure P6.1.33

AB

00

01

11

10

00 01 11 10

0111

d 1 0 d

100 d

010 d

CD

Figure P6.1.34

AB

00

01

11

10

00 01 11 10

1100

0010

0 d dd

0 1 dd

CD

Figure P6.1.35