0195136047.pdf

334 DIGITAL BUILDING BLOCKS AND COMPUTER SYSTEMS

J

K

Ck

Q

Q

D

Ck

Q

Q

T

(a) (b) (c)

Q

Q

Input Output

QQ

Qn Qn

Qn Qn

T

0

1

Figure P6.1.48

Ck

Q

Q

Figure P6.1.49

S

R

“High” switch To logic circuit

Q

Q

Figure P6.1.50

S

R

J A

K B

Feedback loop

Feedback loop

1

Ck

2

Q

Q

Figure P6.1.51

(a)JK= 00

(b)JK= 10

(c)JK= 01

(d)JK= 11

6.1.52Figure P6.1.52 shows the master–slave JKFF. As-
suming that the output changes on the falling edge
of the clock pulse (i.e., when the clock pulse goes
from high to low), discuss the operation of the
flip-flop, and obtain a table indicating the state of
normal outputQafter the passage of one clock
pulse for various combinations of the inputsJK.
6.2.1A table for the direct 3-bit binary decoding is
given. Show a block diagram for a 3-to-8 decoder
and suggest a method for its implementation.

A B C Output = 1

000 F 0

001 F 1

010 F 2

011 F 3

100 F 4

101 F 5

110 F 6

111 F 7

*6.2.2(a)Excess-3 codeis a 4-bit binary code for the

10 decimal digits and is found useful in digi-

tal computer arithmetic. Each combination is

found by adding 3 to the decimal number be-

ing coded and translating the result into direct