0195136047.pdf

396 TRANSISTOR AMPLIFIERS

+

−

VG VDD

R 1

R 2

G

S

D

RS

RD

Figure 8.2.1Method of biasing the JFET.

From Figure 8.2.1, applying the KVL to the loop containingR 2 andRS, the load-line equation is

iD=

VG−vGS

RS

(8.2.3)

The operating pointQis the intersection of the load line with the transfer characteristic, from

whichIDQandVGSQcan be read. While no systematic bias-point design procedure to serve all

applications exists, a simple procedure that will serve a good number of problems is outlined

here. In establishing the operating pointQ, compromising between high stability and high gain,

one may choose

IDQ=

IDSS

3

(8.2.4)

Substituting this into Equation (8.2.2), we get

VGSQ=

(

1 −

√

3

√

3

)

VP∼=− 0. 423 VP (8.2.5)

Next, selectVGto yield a reasonably low slope to the load line so that drain-current changes are

small,

VG= 1. 5 VP (8.2.6)

The voltage drop acrossRSis then given by

VG−VGSQ∼= 1. 5 VP+ 0. 423 VP= 1. 923 VP (8.2.7)

so that

RS=

1. 923 VP

IDQ

=

1. 923 VP

IDSS/ 3

=

5. 768 VP

IDSS

(8.2.8)

ChoosingR 2 arbitrarily as

R 2 = 100 RS (8.2.9)

to maintain large resistance across the gate,R 1 can be found,

R 1 =

R 2 (VDD−VG)

VG

= 100 RS

(

VDD

1. 5 VP

− 1

)

(8.2.10)

Next, to findRD, choosing the transistor’s drop to be equal to that acrossRDplus the pinch-off

voltage necessary to maintain the active-mode operation,

VDD−IDQRS=VP+ 2 IDQRD (8.2.11)