0195136047.pdf

434 DIGITAL CIRCUITS

vout

vin

VOL

VOL

VIL

NML

Transition

width

NMH

VIH VOH

VOH

Figure 9.3.3Typical voltage-transfer character-

istic of a CMOS logic circuit, showing noise mar-

gins.

The switching action in the CMOS circuit is rather sharp, as compared with that of Figure

9.3.1(c). A general voltage-transfer characteristic shown in Figure 9.3.3 illustrates this feature. A

very small change invinis sufficient to produce a relatively large change invout. The voltagesVOH

andVOL, indicated in Figure 9.3.3, are, respectively, the nominal high and low output voltages of

the circuit.VILandVIHare the input voltages at which|dVout/dVin|=1. These are seen to be the

boundaries of the low and high ranges. The region betweenVILandVIHis known as thetransition

region,and thetransition widthis given byVIH−VIL. The lower and uppernoise marginsare

given byVIL−VOL≡NMLandVOH−VIH≡NMH, respectively. The noise margins indicate

the largest random noise voltages that can be added tovin(when it is low) or subtracted fromvin

(when it is high), without yielding an input in the forbidden transition region. A typical voltage-

transfer characteristic and drain currentID 1 versus input voltagevinfor the CMOS inverter are

shown in Figure 9.3.4. Note that whenvinis inside either the low or the high states (and not in

the transition region), the drain currentID 1 =−ID 2 ∼=0. The maximum value ofID 1 that occurs

during transition is indeed very small.

EXAMPLE 9.3.1

For the CMOS inverter with characteristics shown in Figure 9.3.4, determine the noise margins.

Solution

From Figure 9.3.4(a),VOH=7 V andVOL=0. From the location of the approximate points

where the absolute value of the slope is unity,VIL= 3 .1 V andVIH= 3 .9 V. Thus, noise margins

are given by

NML=VIL−VOL∼= 3. 1 − 0 = 3 .1V

NMH=VOH−VIH∼= 7 − 3. 9 = 3 .1V