a third of its thickness is cut off the
back side. This back side is then
prepared so it can be mated to an
outer case (the physical part we
see). It’s here that the electrical con-
tact is made from the back of the
circuit to the external pins.Step 6: Weed out
Bad CPUs
The result of all this work isn’t a
single CPU. The wafers are handled
in batches of about 25 at a time
and each of these pizza-size wafers
holds a little more than 500 CPUs
(called “dies” at this stage), at the
current size of the Pentium 4. While
still on the wafers, the dies are test-
ed to shake out the good from the
bad. No matter how stringent the
pre-testing might have been, most
normal manufacturing processes
allow for about a 10 percent failure
rate. And while no one will talk
directly about the so-called “drop-
out” rate for CPUs built on the
micron scale (as a reference, a peri-
od is about 615 microns wide), you can
expect it to be at least as high. Keep in
mind, however, that “failure” doesn’t
necessarily mean the CPU won’t run at
all, just that it won’t run at its expectedspeed. Some of these dropouts even-
tually become lower-speed versions of
the processor. Convenient, huh?
At this point, the working dies
are sliced by lasers from the wafers,flipped into their ceramic packages,
connected to the pins that will con-
nect the CPU to the motherboard, and
equipped with a heat spreader.
Voila! A CPU is born.MA XIMUMPC NOVEMBER 2004
You Think 90nm Is Small?
By 2011, CPUs will be constructed on a 22nm process. But
a smaller process means bigger headaches for CPU makersToday’s cutting-edge processors use 90nm technology, but
the plan is to get down to 65nm in 2005, and then shrink fur-
ther to 45nm in 2007, 32nm in 2009, and 22nm by 2011. That’s
about a 75 percent reduction in size over just a seven year
period!
A nanometer is one billionth of a meter, which itself is
about 3.3 feet. The reason CPU manufacturers want to shrink
the size of the die is because it’s an easy way to increase
operational speed without increasing the clock speed of the
CPU. This avoids heat issues and a host of other concerns.
Think of it this way: If you had to travel 90 miles and could
go 40mph, it would take you 2.25 hours to make the trip.
Now shorten that distance to 45 miles. Suddenly you only
need 1.3 hours to reach your destination.
If it just dawned on you that making the die smaller while
stuffing more things onto it should present some signifi-
cant engineering challenges, you’re right. If the size of the
die shrinks, the size of the etchings on the die needs to be
reduced as well. This creates some fundamental problems
with the photo-etching process used to manufacture CPUs.When you take a picture, light is used to etch the image
into the negative—or mask, in the case of the CPU. As any
physicist will tell you, light has dimension—width. This width
typically defines the smallest thing you can etch. Using con-
ventional UV light, together with careful planning and correc-
tions for optical distortions in the lenses, it’s possible to print
some features that are slightly smaller than the wavelength
of the UV light itself. But this is not sustainable for long peri-
ods of time, and certainly not down to 22nm.
There is, however, a consortium working on the use of
Extreme Ultraviolet light—the higher frequency, shorter
wavelength side of the UV band of the spectrum, just below
X-rays. Although there are always some tweaks and tricks,
most current CPUs are made with 193nm “deep” UV light
that’s further narrowed by the use of special lenses. Extreme
UV light is so far off on the edge of the spectrum that it pro-
duces 13nm light. The downside is that Extreme UV can’t be
used with conventional lenses. It requires reflective optics—
mirrors essentially—and that means a revamp of equipment,
which means more money. Once this is accomplished, how-
ever, the new process will likely allow chipmakers like Intel
and AMD to continue on down perhaps even to the 5nm
level (via tweaks and tricks again), which should bring us
pretty close to 2017.
And after that? Anyone up for quantum computing?Each wafer is individually examined by a real, live person (in the requisite
bunny suit) for surface defects. Each individual processor on each wafer (of
which there are hundreds) will later be tested for reliability.