FPGA_VIVADO_SI_VHDL_Mihael_Cristian_Ignat

b

begin

if rising_edge(clk) then

q <= d;

end if;

end process;

end Behavioral;

testB_ff.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity testB_ff is
end testB_ff;

architecture Behavioral of testB_ff is
component ff
Port ( clk : in STD_LOGIC;
D : in STD_LOGIC;
Q : out STD_LOGIC);
end component;

signal clk: std_logic := '0';

signal d: std_logic := '0';

signal q: std_logic := '0';

begin

process

begin

clk <= '0';

wait for 5us;

clk <= '1';

wait for 5us;

end process;

process

begin

d <= '0';

wait for 2.95us;

d <= '1';

wait for 2.95us;

end process;