pbegin
HAddr <= HAddr_buf;
VAddr <= VAddr_buf;H_CNT: process(clk)
begin
if rising_edge(clk) then
if HAddr_buf = (HVisibleArea + HFrontPorch_Dim + HSync_Dim + HBackPorch_Dim - 1) then
HAddr_buf <= x"000";
else
HAddr_buf <= HAddr_buf + '1';
end if;
end if;
end process;V_CNT: process(clk)
begin
if rising_edge(clk) then
if HAddr_buf = HVisibleArea + HFrontPorch_Dim + HSync_Dim + HBackPorch_Dim - 1 then
if VAddr_buf = VVisibleArea + VFrontPorch_Dim + VSync_Dim + VBackPorch_Dim - 1 then
VAddr_buf <= x"000";
else
VAddr_buf <= VAddr_buf + '1';
end if;
end if;
end if;
end process;HSync <= '0' when HAddr_buf > HVisibleArea + HFrontPorch_Dim - 1 and
HAddr_buf < HVisibleArea + HFrontPorch_Dim + HSync_Dim else
'1';en_q <= '0' when VAddr_buf > VVisibleArea - 1 else
'0' when HAddr_buf > HVisibleArea - 1 else
'1';VSync <= '0' when VAddr_buf > VVisibleArea + VFrontPorch_Dim - 1 and
VAddr_buf < VVisibleArea + VFrontPorch_Dim + VSync_Dim else
'1';end Behavioral;
testB_sync_vga.vhd
library IEEE;