FPGA_VIVADO_SI_VHDL_Mihael_Cristian_Ignat

y

signal clk : STD_LOGIC := '0';
signal HSync : STD_LOGIC := '0';
signal VSync : STD_LOGIC := '0';
signal R, G, B : STD_LOGIC_VECTOR(3 downto 0) := (others => '0');
begin

clk_gen: process

begin

clk <= not clk;

wait for 7.692 ns;

end process;

uut: VGA_pattern

Port Map(

clk => clk,

R => R,

G => G,

B => B,

HSync => HSync,

VSync => VSync);

end Behavioral;

ROM_character.vhd

-- ROM bitmap

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.numeric_std.all;

--caracterul----- 0 1 2 3 4 5 6 7 8 9.
--pozitia-------- 0 1 2 3 4 5 6 7 8 9 10 11

entity ROM_character is
Port (
clk : in STD_LOGIC;
address: in STD_LOGIC_VECTOR (8 downto 0);
data : out STD_LOGIC_VECTOR (15 downto 0));
end ROM_character;

architecture Behavioral of ROM_character is
type mem is array ( 0 to 287) of std_logic_vector(15 downto 0);
constant my_Rom : mem := (