FPGA_VIVADO_SI_VHDL_Mihael_Cristian_Ignat

cristian i.k_ntxi (Cristian I.K_ntXI) 2023-07-18 10:54:49 UTC #1

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"0000000110110000",

"0000001100110000",

"0000011000110000",

"0000110000110000",

"0001100000110000",

"0001111111111000",

"0000000000110000",

"0000000000110000",

"0000000000110000",

"0000000000110000",

"0000000011111000",

"0000000000000000",

"0000000000000000",

"0011111111111000",

"0011000000000000",

"0011000000000000",

"0011000000000000",

"0011000000000000",

"0011111111110000",

"0000000000011000",

"0000000000001100",

"0000000000001100",

"0000000000001100",

"0000000000001100",

"0000000000001100",

"0000000000011000",

"0011111111110000",

"0000000000000000",

"0000000000000000",

"0000111111110000",

"0001100000000000",

"0011000000000000",

"0011000000000000",

"0011000000000000",

"0011011111110000",

"0011110000011000",

"0011100000001100",

"0011000000001100",

"0011000000001100",

"0011000000001100",

"0011000000001100",

"0001100000011000",

"0000111111110000",

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