jjC : out STD_LOGIC_VECTOR (6 downto 0));
end component;
component shift_reg is
Generic(number_of_FF: integer := 16);
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
ce : in STD_LOGIC;
rot : in STD_LOGIC;
load : in STD_LOGIC;
load_data : in STD_LOGIC_VECTOR (number_of_FF - 1 downto 0);
data : out STD_LOGIC_VECTOR (number_of_FF - 1 downto 0);
q : out STD_LOGIC);
end component;
component uart_tx is
generic(
system_clock: integer;
baud_rate: integer);
port (
clk:in std_logic;
tx: out std_logic;
data_send: in std_logic_vector(7 downto 0);
start_send: in std_logic;
done: out std_logic
);
end component;
signal clk65MHz : STD_LOGIC := '0';
signal adrChar : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
signal adrLine : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
signal adrCol : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
signal ROM_extract_pixel_q : STD_LOGIC := '0';
signal R_pattern : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
signal G_pattern : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
signal B_pattern : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
signal HAddr : STD_LOGIC_VECTOR (11 downto 0) := (others => '0');
signal VAddr : STD_LOGIC_VECTOR (11 downto 0) := (others => '0');
signal ssd_data: STD_LOGIC_VECTOR (15 downto 0) := x"1234";
signal shift_reg_ce : STD_LOGIC := '0';
signal shift_reg_load : STD_LOGIC := '1';
signal shift_reg_load_data : STD_LOGIC_VECTOR (15 downto 0) := x"1234";
type uart_data_type is array ( 0 to 11) of character;
constant uart_data_array: uart_data_type := ("Hello world") & LF;
signal char_converted: std_logic_vector(7 downto 0) := (others => '0');
signal uart_data_send: STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal uart_start_send: STD_LOGIC := '0';