FPGA_VIVADO_SI_VHDL_Mihael_Cristian_Ignat

ll

adrCol => HAddr(3 downto 0),

q => ROM_extract_pixel_q

);

vga_patt: VGA_pattern
Port Map(
clk => clk65MHz,
R => R_pattern,
G => G_pattern,
B => B_pattern,
HAddr => HAddr,
VAddr => VAddr,
HSync => HSync,
VSync => VSync,
en_q => vga_en_q
);

-- numarator pentru a schimba la fiecare secunda valoarea
process(clk65MHz)
begin
if rising_edge(clk65MHz) then
if rst = '1' then
ssd_display_counter <= x"0000_0000";
ssd_data <= x"0123";
else
if ssd_display_counter < x"03DF_D23F" then
ssd_display_counter <= ssd_display_counter + '1';
else
ssd_display_counter <= x"0000_0000";
ssd_data <= ssd_data + x"1111";
end if;

if ssd_data(15 downto 12) = "1010" then
ssd_data <= x"0123";
elsif ssd_data(3 downto 0) = "1010" then
ssd_data <= x"3210";
end if;
end if;
end if;
end process;

ssd: SSD_CTRL
Generic Map(number_of_digits => 4)
Port Map(
clk => clk65MHz,
data => ssd_data,
AN => an,
C => seg
);