FPGA_VIVADO_SI_VHDL_Mihael_Cristian_Ignat

qq

set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}]
set_property PACKAGE_PIN R2 [get_ports {sw[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}]

Generate.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity generate_test is
Generic (reg_width: in integer := 2);
Port ( CLK100MHZ : in STD_LOGIC;
sw : in STD_LOGIC_VECTOR (3 downto 0);
LED : out STD_LOGIC_VECTOR (3 downto 0));
end generate_test;

architecture Behavioral of generate_test is
component reg
Generic( data_width: positive := 4);
Port ( clk : in STD_LOGIC;
D : in STD_LOGIC_vector(data_width - 1 downto 0);
Q : out STD_LOGIC_vector(data_width - 1 downto 0));
end component;

type data_arr is array (NATURAL range <>) of std_logic_vector(3 downto 0);

signal data_in: data_arr(reg_width - 1 downto 0);

signal data_out: data_arr(reg_width - 1 downto 0);

attribute keep : string;

attribute keep of data_in: signal is "true";

attribute keep of data_out: signal is "true";

begin
data_in(0) <= sw;
led <= data_out(reg_width - 1);

reg_generated:
for i in 0 to (reg_width - 1) generate
REGX : reg port map
(clk => CLK100MHZ,
d => data_in(i),
q => data_out(i)
);

data_in_gen: if i < reg_width - 1 generate

process(CLK100MHZ)

begin

if(CLK100MHZ'event and CLK100MHZ = '0') then

data_in(i + 1) <= data_in(i) xnor data_out(i);

end if;