FPGA_VIVADO_SI_VHDL_Mihael_Cristian_Ignat

ss

led_shift_counter <= led_shift_counter + '1';

shift_reg_ce <= '0';

else

led_shift_counter <= x"0000_0000";

shift_reg_ce <= '1';

end if;

end if;

end if;

end process;

shift_r: shift_reg

Generic Map(number_of_FF => 8)

Port Map(

clk => CLK100MHZ,

rst => rst,

ce => shift_reg_ce,

rot => '1',

load => shift_reg_load,

load_data => shift_reg_load_data,

data => shift_reg_q);

q_func <= add_f(sw(15 downto 13), sw(12 downto 10));

sub_p(sw(15 downto 13), sw(12 downto 10), q_proc);

end Behavioral;

pkg_exp.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

package pkg_exp is
CONSTANT WIDTH_LIMIT : positive := 3;
subtype data_type is std_logic_vector(WIDTH_LIMIT - 1 downto 0);

function add_f (A,B: data_type) return data_type;

procedure sub_p (signal A: in data_type; signal B: in data_type; signal Q: out data_type);

component shift_reg is
Generic(number_of_FF: integer := 16);
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
ce : in STD_LOGIC;
rot : in STD_LOGIC;
load : in STD_LOGIC;
load_data : in STD_LOGIC_VECTOR (number_of_FF - 1 downto 0);
data : out STD_LOGIC_VECTOR (number_of_FF - 1 downto 0);
q : out STD_LOGIC);
end component;
end;
package body pkg_exp is