Computing technologies: platforms, processors, and controllers Chapter | 3 35The combination of a real-time multicore processor specially designed for
the automotive domain (e.g., with respect to power consumption, inference
capabilities, speed, etc.) with general-purpose HPC processors and accelerators
will allow the development of powerful data fusion platforms that can support
any future automotive scenario. This embedded high-performance computing
(eHPC) platform will be the basis for more applications that require security,
safety and high-performance, and the automotive example will be the reference
for other domains including industry, medical, and machinery (Bello, Mariani,
Mubeen, & Saponara, 2018).
In the automotive scenario, various alternatives must be examined.
Alternative must combine the use of the multicore architecture with the accel-
erators and the HPC processors, offer fast interfacing between the two, and
adapt existing models, algorithms, and software architectures to this distributed
processing environment. The new environment allows the implementation of
various automotive application scenarios in a distributed onboard and off-board
computation environment (e.g., management of traffic information can be done
off-board, whereas real-time routing decisions making modules onboard can
take advantage of the off-board processing results and current conditions from
onboard sensors). Among the requirement for the efficient interaction between
onboard and back-end off-line components will be the establishment of secure
and reliable communications, the management and verification of device iden-
tity, and the privacy of data providers in collective scenarios (e.g., in traffic
reporting and management applications). This implies the need for joined
design and development of HW and SW and the embedding of safety and secu-
rity mechanisms and processes in the automotive eHPC platform.
According to the automotive functional safety standard (ISO 26262) various
levels of automotive safety integrity (ASIL) have been defined ranging from A
to D, which is the highest degree of safety against hazard. In the ASIL-B level,
the integrity check is based on some safety mechanisms [ECC in memory, parity
in caches, CRC in network on chip (NoC)], which evaluate the proper operation
of processors. In the ASIL-D level, the integrity of processors is mainly checked
by performing redundant computations. The results of these computations are
compared to the expected results in order to verify integrity and comparisons
are performed by the safe microcontroller, which is dedicated to the task (Bello
et al., 2018). The safe micro-controller monitors computations and is respon-
sible for granting trust to the results.
As a result, the vision for the next-generation automotive platform assumes
a combination of the main automotive SoC, an HPC-general purpose proces-
sor, and several attached accelerators, which are capable to control the whole
perception process of an AD system. The main SoC will act as safe micro-
controllers that communicate with the vehicle backend processor, which pro-
vides a run-time environment that is compliant with the Classic AUTOSAR
(AUTomotive Open System ARchitecture). Two or more “safe number crunch-
ers” will apply parallel computing and directly access sensor data through