the circuits and logic required to control eight IRQ lines. Figure 13-11 illustrates the gen-
eral design of a PIC. It is called aprogrammable controllerbecause chipset, processor, and
motherboard manufacturers can program the chip and address each of its registers to fit a
particular purpose or function.
Figure 13-11 shows how the PIC works in general. The individual IRQ lines have one
interrupt mask register (IMR) and two interrupt status registers, which are named PIC1
and PIC2. The IRQ enters the PIC through its IMR, which determines if the IRQ is masked
(disabled) and if it is, the request is ignored. If the IRQ is not masked, the request is recorded
in the interrupt request register (IRR). The IRR holds the IRQ requests until after they have
beenprocessedoracknowledged,dependingontheserviceoractionrequested. The priority
resolver (PR) acts as a sort of traffic co pto ensure that the highest priority request is han-
dled first. IRQ priority is essentially the lowest number first. Once the IRQs are prepared
for processing, the CPU is notified on its INT (interrupt) line that requests are pending
and,assoonasitcompletesitscurrenttask,theCPUrespondswithaninterruptacknowl-
edgment (INTA).
After the CPU acknowledges the INT query, the active IRQ is placed in the in-service
register (ISR) that holds the IRQ currently being processed. The fact that this IRQ is being
serviced is also updated in the IRR and the applicable ISR. The address of the IRQ is sent
to the CPU, and the IRQ is serviced. When the requested activity is completed, the ISR
Chapter 13: System Resources^297
Figure 13-11. The components of a programmable interrupt controller