Digital Logic Fundamentals Unit 6 – JK Flip-Flop
UNIT 6 – JK FLIP-FLOP
UNIT OBJECTIVE
When you have completed this unit, you will be able to demonstrate the operation and
configurations of a JK flip-flop by using the DIGITAL LOGIC FUNDAMENTALS circuit
board.
UNIT FUNDAMENTALS
The schematic symbol shows a JK flip-flop. There are two data inputs (J and K) and a clock
input. This JK flip-flop requires a negative clock edge signal; however, other JK flip-flops may
require a positive clock edge, a logic 1, or a logic 0 clock signal.
In addition, there usually are asynchronous preset and clear inputs to respectively set and reset
the JK flip-flop. Either negative (as shown) or positive logic levels may be required
at PR or CLR. The outputs, Q and Q, are complementary.
The JK flip-flop is the most commonly used flip-flop because it is versatile.
The JK flip-flop can be adapted to have the operating features of an RS flip-flop, a T flip-flop
(toggle flip-flop), a D-type flip-flop, or a master-slave JK flip-flop.
The basic JK flip-flop is essentially a clocked RS flip-flop; the J and K inputs are equivalent to
the R and S inputs, respectively.