Digital Logic Fundamentals Unit 6 – JK Flip-Flop
Exercise 2 – Dynamic Operation of a JK Flip-Flop
EXERCISE OBJECTIVE
When you have completed this exercise, you will be able to configure a JK flip-flop to operate as
a toggle flip-flop or a D-type flip-flop by using the DIGITAL LOGIC FUNDAMENTALS
circuit board. You will verify your results by comparing the input and output logic states.
EXERCISE DISCUSSION
- The JK flip-flop is the most commonly used flip-flop because it can be configured to have
the operating features of an RS flip-flop, a T flip-flop, or a D-type flip-flop. - In the previous exercise, you observed that a JK flip-flop is essentially a clocked RS flip-
flop. - In this exercise procedure, you will configure the JK flip-flop as a T flip-flop and as a D-type
flip-flop; a 50 kHz clock signal is used. - When the J and K data inputs are each set at logic 1, the JK flip-flop functions as a T flip-
flop.
• The Q and Q outputs of a T flip-flop change state (toggle) at every negative edge of the
clock signal.- However, if the PR or CLR inputs are logic 0, the toggle action of the outputs with the clock
signal is overridden, and the outputs are held in the set or reset state.
• The J, K, PR, and CLR inputs of the JK flip-flop are logic 1. The Q and Q outputs will
change state at every negative edge of the clock signal because the JK flip-flop is configured
as a T flip-flop.- A timing diagram shows the relationship between the CLK signal and the Q and Q-not output
signals. Q and Q toggle (change state) at every negative edge of the clock signal.
• Because Q and Q are complementary, Q is logic 1 when Q is logic 0 and vice versa.
• The Q and Q signals have one cycle for every two clock cycles.
• The Q and Q frequencies are each half of the CLK frequency because they change logic
states only on the negative edge of CLK.• During the positive edge of CLK, Q and Q do not change logic states.
• If the frequency of the CLK signal is 50 kHz, the frequency of the Q and Q outputs is 25
kHz.- When the J input to the JK flip-flop is inverted and connected to the K input, the J and K
inputs are always complementary. - In Unit 5, you demonstrated that the Q output of a D-type flip-flop equals the logic state of
the D input (J input) after every clock signal (negative edge). - To configure a JK flip-flop as a D-type flip-flop, the J input is inverted and connected to the
K input.