8.7. DESIGN ISSUES IN HFETS 395
the distributed charge as a 2 dimensional sheet charge of densityensa distanceΔdfrom the
heterointerface, whereΔdis the centroid of the charge distribution.
To find our 2DEG carrier densityns, we follow the same methodology as in our MODFET
analysis (see equation 8.5.5). Doing this, we get
φs−V 1 −ΔEc
e+Vdi−=0 (8.6.11)whereVdi−was given in equation 8.5.3 andV 1 is given by
V 1 =
[Qπ(net)−ens]dAlGaN
(8.6.12)
Substituting these values into equation 8.6.11 and settingdAlGaN+Δd=Dgives us forns
ns=Qπ(net)·dAlGaN−(φs−ΔEc/e)
eD(8.6.13)
which is the same expression as that derived for conventional HFETs withds=0(i.e. with
the donor sheet at the heterointerface). This is reassuring, since in the case of AlGaN/GaN
heterostructures, the positive sheet charge that induces the 2DEG is the net polarization charge at
the heterointerface. The physical difference between conventional and polar HFETs is simply the
origin of the electrons in the 2DEG. In conventional HFETs, the channel electrons are provided
by a donor sheet, while in GaN-based HFETs, they come from ionized surface donor states.
In an HFET structure, we place a gate metal on top of the AlGaN layer and apply a gate
voltage to modulate the charge in the 2DEG. The only difference between the HFET charge
control analysis and the one presented here for an AlGaN/GaN heterostructure is that in the
HFET, the potential barrier at the metal/AlGaN interface is given byφb−VG,whereφbis the
metal-semiconductor barrier height andVGis the applied gate voltage. Thus, for the AlGaN/GaN
HFET, the 2DEG sheet charge density as a function of gate voltage can be written as
ns(VG)=Qπ(net)·dAlGaN+[VG−(φb−ΔEc/e)]
eD(8.6.14)
8.7 DESIGNISSUESINHFETS............................
In addition to the issue of aspect ratio discussed for MESFETs and JFETs in Chapter 8, there
are several other design issues to be considered in HFETs. They are summarized in table 8.1.
We will discuss a number of techniques which are employed in modern HFET processes that
address these issues.
8.7.1 n+Cap Layers ...............................
n+cap layers are used to reduce the contact resistance as well as the access resistance in
the device. The schematic of an AlGaAs/GaAs HFET with ann+GaAs cap layer is shown in