Handbook for Sound Engineers

Consoles 941

arrangement as in Fig. 25-111 emerges, which is our old
friend the Superbal differential summing arrangement
fed by both DACs being driven differentially. Not only
does this provide a gain-control stage with full-rail
differential signal-handling capability, but also the
charge-injection noise is substantially canceled. To get
the best noise cancellation, however, the DACs really
need to be matched (a DCR test through the ladder is a
reasonable guide for matching) or pairs on the same
substrate employed.

25.16.3.3 Zero-Crossing

The second impulse noise cause is attempting to switch
a high-value signal; any truncated or very rapidly
level-shifted high-level signal is going to go “click!”
(Run tone through a switch and turn it on and off a few
times. The switch click—nicknamed tone-click—will

vary in intensity seemingly at random; that’s because

the switching is occurring at random points through the

sine wave’s cycle. Those at or near the crests of the sine

wave will click loudest.) The simple solution is, don’t.

If one arranges only to change gain while the applied

signal is crossing through zero or is at a low level, this

manifestation will all but disappear.

This is a control issue rather than an audio path issue;

Fig. 25-111 illustrates differential MDACs with a periph-

eral circuit that achieves near zero-crossing. The

MDACs in Figs. 25-110 and 25-111 are double-buff-

ered. In other words, it is possible to load a new gain

value into them without disturbing the current opera-

tional gain and then transfer the new value over when

desired by means of the /LD control pin. The arrange-

ment shown allows the controlling micro to do a “hit and

run” on the circuit, depositing the new gain data and

telling the circuit to take it at the next zero-crossing; the

micro doesn’t have to hang around waiting for a

Figure 25-111. Differential MDAC gain control, with zero-crossing enable.

+5 V

+5 V

+15 V

+5 V

+15V

++

+

+

SRI

SRI

CLK

CLK

1OUT

/LD

1 OUT

8043

0

/LD

8043

1.2 M

6 k8

0

1.2 M

Input

Serial Data

Serial Clock

Input

3.0 k

2.7 k

+

1

2

+

3.0 k

44 k

'ARM'

3 k9

33 k

100 MF

150 pF

10 pF

++

100 MF

1 k5

10 k

NE

5532

1 k

22 k 6.8 k 100

1.1 k

6.8 k

+5V

IN4148

LM339

Quad comparator

10 k

150 pF

+