VHDL Programming

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Chapter 6 Predefined Attributes This chapter discusses VHDL predefined attributes and the way that concise readable models can b ...

144 Chapter Six Predefined attributes have a number of very important applications. Attributes can be used to detect clock edges ...

Predefined Attributes 145 The left bound of a type or subtype is the leftmost entry of the range constraint. The right bound is ...

146 Chapter Six -- returns 0 END PROCESS; This example shows how the different attributes can be used to return information abou ...

Predefined Attributes 147 of a value are equal to the value itself; but for an enumerated type, the position numbers of a value ...

148 Chapter Six CONSTANT andsd : t_4valX2 := ((’x’, -- xx ’ 0 ’, -- x0 ’x’, -- x1 (Notice this is an ’x’), -- xz array of arrays ...

Predefined Attributes 149 len3 := t_4valmd’LENGTH(1); -- returns 4 len4 := t_4valmd’LENGTH(2); -- returns 4 END PROCESS; Type t_ ...

150 Chapter Six LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; ENTITY shifter IS PORT( clk, left : IN std_logic; right : OUT std_log ...

Predefined Attributes 151 For any block or architecture that does not contain any component instantiation statements, attribute ...

152 Chapter Six A typical use of a function type attribute is to convert from an enu- merated or physical type to an integer typ ...

Predefined Attributes 153 END PROCESS; END behave; Package ohms_lawdeclares three physical types used in this example. Types cur ...

154 Chapter Six color’RIGHTOF (blue) returns purple. color’LEFTOF(green) returns yellow. reverse_color’RIGHTOF(blue) returns ...

Predefined Attributes 155 For descending ranges, the opposite is true: array’LEFT = array’HIGH array’RIGHT = array’LOW Following ...

156 Chapter Six IF (addr = x_val) OR (addr = z_val) THEN ASSERT FALSE REPORT “ writing to unknown address” SEVERITY ERROR; data ...

Predefined Attributes 157 transition, or what the previous value of the signal was. There are five attri- butes that fall into t ...

158 Chapter Six changed, then a rising edge must have occurred. (When a synthesis tool is applied to the preceding example, a fl ...

Predefined Attributes 159 Setup Time Hold Reference Clock Edge Time DATA CLK Figure 6-1 Setup and Hold Time Waveform Descrip- ti ...

160 Chapter Six The passive process executes for each event on signal clk. When the clkinput has a rising edge, the ASSERTstatem ...

Predefined Attributes 161 One restriction on the use of these attributes is that they cannot be used within a subprogram. A comp ...