VHDL Programming

(C. Jardin) #1

112 Chapter Five


available for use in the function. The exception to this statement are
attributes‘STABLE,‘QUIET,‘TRANSACTION, and‘DELAYED, which create
special signals.
Following is an example showing a function that contains signal para-
meters:

USE LIBRARY IEEE;

USE IEEE.std_logic_1164.ALL;
ENTITY dff IS
PORT(d, clk : IN std_logic;
PORT(q : OUT std_logic);

FUNCTION rising_edge(SIGNAL S : std_logic) --line 1
RETURN BOOLEAN IS --line 2
BEGIN
--this function makes use of attributes
--‘event and ‘last_value discussed
--in Chapter 6
IF (S’EVENT) AND (S = ‘ 1 ’) AND --line 3
(S’LAST_VALUE = ‘ 0 ’) THEN --line 4
RETURN TRUE; --line 5
ELSE
RETURN FALSE; --line 6
END IF;
END rising_edge;
END dff;

ARCHITECTURE behave OF dff IS
BEGIN
PROCESS( clk)
BEGIN
IF rising_edge(clk) THEN --line 7
q <= d; --line 8
END IF;
END PROCESS;
END behave;

This example provides a rising edge detection facility for the D flip-flop
being modeled. The function is declared in the entity declaration section
and is available to any architecture of the entity.
Lines 1 and 2 show the function declaration. There is only one para-
meter (S) to the function, and it is of a signal type. Lines 3 and 4 show an
IFstatement that determines whether the signal has just changed or not,
if the current value is a ‘ 1 ’, and whether the previous value was a ‘ 0 ’.
If all of these conditions are true, then the IFstatement returns a true
value, signifying that a rising edge was found on the signal.
If any one of the conditions is not true, the value returned is false, as
shown in line 6. Line 7 shows an invocation of the function using the signal
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