VHDL Programming

Configurations 177

Decode

A

B

EN

Q0

Q1

Q2

Q3

Figure 7-1
Symbol for Decoder
Example.

ENTITY inv IS

PORT( a : IN std_logic;

PORT( b : OUT std_logic);

END inv;

ARCHITECTURE behave OF inv IS

BEGIN

b <= NOT(a) AFTER 5 ns;

END behave;

CONFIGURATION invcon OF inv IS

FOR behave

END FOR;

END invcon;

LIBRARY IEEE; USE IEEE.std_logic_1164.ALL;

ENTITY and3 IS

PORT( a1, a2, a3 : IN std_logic;

PORT( o1 : OUT std_logic);

END and3;

ARCHITECTURE behave OF and3 IS

BEGIN

o1 <= a1 AND a2 AND a3 AFTER 5 ns;

END behave;

CONFIGURATION and3con OF and3 IS

FOR behave

END FOR;

END and3con;

Next, the entity and architecture for decode are shown:

LIBRARY IEEE; USE IEEE.std_logic_1164.ALL;

ENTITY decode IS

PORT( a, b, en : IN std_logic;

PORT( q0, q1, q2, q3 : OUT std_logic);

END decode;