176 Chapter Seven
16-bit counter. The architectures specify a synchronous counter with a
synchronous loadand clear. All operations for the device occur with respect
to the clock.
Each of the two configurations for the entity specifies a different
architecture for the counter entity. Let’s examine the first configuration
in more detail. The configuration design unit begins with the keyword
CONFIGURATIONand is followed by the name of the configuration. In this
example, the name of the configuration is small_count. The keyword OF
precedes the name of the entity BEGINconfigured (counter). The next line
of the configuration starts the block configuration section. The keyword
FORis followed by a name of the architecture to use for the entity being
configured or the name of the block of the architecture that will be config-
ured. Any component or block configuration information then exists
between the FOR ARCHITECTUREclause and the matching END FOR.
In this architecture, there are no blocks or components to configure;
therefore, the block configuration area from the FORclause to the END
FORclause is empty, and the default is used. The configuration is called
the default configuration, because the default is used for all objects in
the configuration.
The first configuration is called small_countand binds architecture
count_255with entity counterto form a simulatable object. The second
configuration binds architecture count_64kwith entity counter and
forms a simulatable object called big_count.Component Configurations
In this section, we discuss how architectures that contain instantiated
components can be configured. Architectures that contain other compo-
nents are called structural architectures. These components are config-
ured through component configuration statements.
Let’s first look at some very simple examples of component configura-
tions, and then at some progressively more complex examples. The first
example is a simple 2 to 4 decoder device. Figure 7-1 shows the symbol
for the decoder, and Figure 7-2 shows the schematic.
The components used in the design are defined using the VHDL descrip-
tion shown here:LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;