182 Chapter Seven
no other mapping needs to take place. The default mapping causes the
ports to match. What happens when the component ports do not match
the entity being mapped to the component instance? Without any further
information, the compiler cannot figure out which ports to map to which
and produces an error. However, more information can be passed to the
compiler with the configuration port map clause.
The configuration port map clause looks exactly like the component
instantiation port map clause used in an architecture. The configuration
port map clause specifies which of the component ports map to the actual
ports of the entity. If the port names are different, then the port map
clause specifies the mapping.
Let’s change the port names of the invcomponent used in the previous
example and see what the effect is in the configuration:LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY inv IS
PORT( x : IN std_logic;
PORT( y : OUT std_logic);
END inv;ARCHITECTURE behave OF inv IS
BEGIN
y <= NOT(x) AFTER 5 ns;
END behave;CONFIGURATION invcon OF inv IS
FOR behave
END FOR;
END invcon;The entity and architecture for decodestays exactly the same, including
the component declaration. The configuration, however, needs to add the
port map clause, as shown in the following example:CONFIGURATION decode_map_con OF decode IS
FOR structural
FOR I1 : inv USE ENTITY WORK.inv(behave);
PORT MAP( x => a, y => b );
END FOR;FOR I2 : inv USE ENTITY WORK.inv(behave);
PORT MAP( x => a, y => b );
END FOR;FOR ALL : and3 USE ENTITY WORK.and3(behave);