VHDL Programming

184 Chapter Seven

END behave;

CONFIGURATION and2con OF and2 IS

FOR behave

END FOR;

END and2con;

Two of these can be connected with the entity architecture shown be-

low to form a structural representation of the 3-input AND gate.

LIBRARY IEEE;

USE IEEE.std_logic_1164.ALL;

ENTITY

struc_and3 IS

PORT( I1, I2, I3 : IN std_logic;

PORT( O1 : OUT std_logic);

END struc_and3;

ARCHITECTURE structural OF struc_and3 IS

COMPONENT and2

PORT( a, b : in std logic;

c : out std logic );

END COMPONENT;

SIGNAL s1, s2 : std_logic;

BEGIN

X1 : and2

PORT MAP( a => I1, b => I2, c => s1 );

X2 : and2

PORT MAP( a => I3, b => s1, c => O1 );

END structural;

This architecture can then be configured with the following configuration:

CONFIGURATION and3strc con OF struc and3 IS

FOR structural

FOR X1 : and2 USE CONFIGURATION WORK.and2con;

END FOR;

FOR X2 : and2 USE CONFIGURATION WORK.and2con;

END FOR;

END FOR;

END and3strc con;

Now, configuration decode_map_conof entity decode, described earlier,

can be modified as follows: