VHDL Programming

Configurations 193

SIGNAL nota, notb : std_logic;

BEGIN

I1 : inv

PORT MAP( a, nota);

I2 : inv

PORT MAP( b, notb);

AN1 : and3

PORT MAP( nota, en, notb, q0);

AN2 : and3

PORT MAP( a, en, notb, q1);

AN3 : and3

PORT MAP( nota, en, b, q2);

AN4 : and3

PORT MAP( a, en, b, q3);

END structural;

Notice that the component declarations for components invand and3

in the architecture declaration section do not contain the generics

declared in the entity declarations for entities invand and3. Because the

generics are not being mapped in the architecture, there is no need to

declare the generics for the components in the architecture.

Following is the configuration to bind all of these parts together into

an executable model:

CONFIGURATION decode_gen1_con OF decode IS

FOR structural

FOR I1 : inv USE ENTITY WORK.inv(inv_gen1)

GENERIC MAP( int_rise => 1.2 ns,

GENERIC MAP( int_fall => 1.7 ns,

GENERIC MAP( ext_rise => 2.6 ns,

GENERIC MAP( ext_fall => 2.5 ns);

END FOR;

FOR I2 : inv USE ENTITY WORK.inv(inv_gen1)

GENERIC MAP( int_rise => 1.3 ns,

GENERIC MAP( int_fall => 1.4 ns,

GENERIC MAP( ext_rise => 2.8 ns,

GENERIC MAP( ext_fall => 2.9 ns);

END FOR;

FOR AN1 : and3 USE ENTITY WORK.and3(and3_gen1)

GENERIC MAP( int_rise => 2.2 ns,

GENERIC MAP( int_fall => 2.7 ns,

GENERIC MAP( ext_rise => 3.6 ns,

GENERIC MAP( ext_fall => 3.5 ns);

END FOR;