VHDL Programming

196 Chapter Seven

board-socket-chip analogy. (This analogy was originally presented to me

by Dr. Alec Stanculescu.) In this analogy, the architecture of the top-level

entity represents the board being modeled. The component instance repre-

sents a socket on the board, and the lower-level entity being instantiated

in the architecture represents the chip.

This analogy helps describe how the ports and generics are mapped at

each level. At the board (architecture) level component socket pins are

interconnected with signals. The chip pins are then connected to socket

pins when the chip is plugged into the socket. Following is an example of

how this works:

LIBRARY IEEE;

USE IEEE.std_logic_1164.ALL;

Declarations / Mapping

D

N

X

A

Declared, with default value

Declared, with no default value

Not Declared

Actual Mapped

Errors / Warnings

1 Can only map generic in configuration if declared in the entity

2 Generic declared in component but not in entity, hence it is not used

3 Can only map generic in component instance if declared in component declarations

4 Can’t map a generic in the component instance and the configuration

5 Must map at least one generic to get the default value for other generics

Generic Values

E

M

I

C

Default taken from entity

Default taken from configuration

Actual taken from component instance

Actual taken from configuration

Figure 7-4
Configuration
Generic Table Transla-
tions.