204 Chapter Seven
SUMMARY
In this chapter, we discussed the following:How default configurations can be used to bind architectures to
entities.How component configurations can be used to specify which entity
to use for each component instantiation.How port maps within configurations allow mapping entities with
different names to component instances.How generics can be specified in configurations to allow late
binding of generic information.How block configurations can be used to configure architectures
with block statements in them.How architecture configurations allow specification of configurations
for component instantiations in the architecture declaration section.The basic features of VHDL have now been introduced. In the next
chapter, we examine some of the more esoteric but useful features that
exist in VHDL.