VHDL Programming

Advanced Topics 221

DQ

CLK

DQ

CLK

DQ

CLK

DQ

CLK

CLK

DFFX(0) DFFX(1) DFFX(2) DFFX(3)

Z(0) Z(1) Z(2) Z(3) Z(4)

A B

CLK

Figure 8-1
Schematic Represent-
ing Generate State-
ment.

END GENERATE;

b <= z(4);

END gen_shift;

This example represents the behavior for a 4-bit shift register. Port a

is the input to the shift register, and port bis the output. Port clkshifts

the data from ato b.

Architecture gen_shiftof entity shiftcontains two concurrent signal

assignment statements and one GENERATEstatement. The signal assign-

ment statements connect the internal signal zto input port aand output

port b. The generate statement in this example uses a FORscheme to gen-

erate four DFF components. The resultant schematic for this architecture

is shown in Figure 8-1.

The FOR in the generate statement acts exactly like the FOR loop

sequential statement in that variable ineed not be declared previously,

iis not visible outside the generate statement, and icannot be assigned

inside the generate statement.

The result of the generate statement is functionally equivalent to the

following architecture:

ARCHITECTURE long_way_shift OF shift IS

COMPONENT dff

PORT( d, clk : IN std_logic;

PORT( q : OUT std_logic);

END COMPONENT;

SIGNAL z : std_logic_vector( 0 TO 4 );

BEGIN

z(0) <= a;

dff1: dff PORT MAP( z(0), clk, z(1) );

dff2: dff PORT MAP( z(1), clk, z(2) );

dff3: dff PORT MAP( z(2), clk, z(3) );

dff4: dff PORT MAP( z(3), clk, z(4) );