Advanced Topics 223
IF i = 0 GENERATE
dffx : dff PORT MAP( a, clk, z(i + 1));
END GENERATE;IF i = (len -1) GENERATE
dffx : PORT MAP( z(i), clk, b );
END GENERATE;IF (i > 0) AND i < (len -1) GENERATE
dffx : PORT MAP( z(i), clk, Z(i + 1) );
END GENERATE;END GENERATE;
END if_shift;This example uses a shift register that has a configurable size. Generic
lenpassed in specifies the length of the shift register. (Generic lenmust be
at least 2 for the shift register to work properly.) Generic lenis used in
the specification of the length of signal array z. This type of array is known
as a generically constrained array because the size of the array is specified
through one or more generics.
The FORclause of the generate also uses generic lento specify the
maximum number of DFFcomponents to be generated. Notice that this
generate statement uses the conditional form of the generate statement.
If the condition is true, the concurrent statements inside the generate
statement are generated; otherwise, nothing is generated.
The first IF-THENcondition checks for the first flip-flop in the shift
register. If this is the first flip-flop, notice that the port map clause maps
the input signal adirectly to the flip-flop instead of through an interme-
diate signal. The same is true of the next IF-THENcondition. It checks for
the last flip-flop of the shift register and maps the last output to output
port b. Any other flip-flops in the shift register are generated by the third
conditional generate statement.
Following is another interesting example using the conditional gener-
ate statement:PACKAGE gen_cond IS
TYPE t_checks IS ( onn, off);
END gen_cond;USE WORK.gen_cond.ALL;LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY dff IS
GENERIC( timing_checks : t_checks;