VHDL Programming

274 Chapter Eleven

Design Specification

HDL Capture

RTL Simulation

RTL Synthesis

Functional

Gate Simulation

Place and Route

Post Layout Timing

Simulation

Static Timing Analysis

Figure 11-1
High-Level Design
Flow.

After the specification has been completed, the designer or designers can

begin the process of implementation. Some design teams create a high- level

behavioral or algorithmic description of the design to verify design intent,

then convert that description to RTL (Register Transfer Level) later. How-

ever, most design teams skip the behavioral description and implement the

RTL directly. The RTL is created during the HDL capture step. The de-