VHDL Programming

304 Chapter Thirteen

Reg0

Reg1

Reg2

Reg3

Reg7

Regsel

ProgCnt

AddrReg

Addr(15:0) Data(15:0)

ALU

Control

Ready R/W VMA

Shifter

Shiftsel

Alusel

OutReg

Progsel

Addrsel

Outsel

OpReg

OpRegsel

InstrReg

Instrsel

Clock

Reset

Comp

Compsel

CompoutCompout

Figure 13-1
CPU Block Diagram.

Following is an implementation of this block diagram, shown by file

cpu.vhd:

library IEEE;

use IEEE.std_logic_1164.all;

use work.cpu_lib.all;

entity cpu is

port(clock, reset, ready : in std_logic;

port(addr : out bit16;

port(rw, vma : out std_logic;

port(data : inout bit16);

end cpu;

architecture rtl of cpu is

component regarray

port( data : in bit16;

port( sel : in t_reg;

port( en : in std_logic;

port( clk : in std_logic;

port( q : out bit16);

end component;