VHDL Programming

306 Chapter Thirteen

port( sel : in t_comp;

port( compout : out std_logic);

end component;

signal opdata, aluout, shiftout, instrregOut : bit16;

signal regsel : t_reg;

signal regRd, regWr, opregRd, opregWr, outregRd, outregWr,

signal addrregWr, instrregWr, progcntrRd, progcntrWr,

signal compout : std_logic;

signal alusel : t_alu;

signal shiftsel : t_shift;

signal compsel : t_comp;

begin

ra1 : regarray port map(data, regsel, regRd, regWr, data);

opreg: trireg port map (data, opregRd, opregWr, opdata);

alu1: alu port map (data, opdata, alusel, aluout);

shift1: shift port map (aluout, shiftsel, shiftout);

outreg: trireg port map (shiftout, outregRd, outregWr,

data);

addrreg: reg port map (data, addrregWr, addr);

progcntr: trireg port map (data, progcntrRd, progcntrWr,

data);

comp1: comp port map (opdata, data, compsel, compout);

instr1: reg port map (data, instrregWr, instrregOut);

con1: control port map (clock, reset, instrregOut, com

pout, ready, progcntrWr, progcntrRd, addrregWr, out

regWr, outregRd, shiftsel, alusel, compsel, opre

gRd, opregWr, instrregWr, regsel, regRd, regWr, rw,

vma);

end rtl;

Architecture rtlof entity cpuis a structural implementation of the

block diagram. Architecture rtlcontains the component declarations of all

of the components used to build the design, the signals used to connect the

components, and the component instantiations to create the functionality.

After the component and signal declarations are the component instan-

tiation statements that instance the components and connect the appro-

priate signals. In the next few sections, each of the VHDL component

descriptions is described in more detail.

ALU

The first entity described is the ALU. This entity performs a number of

arithmetic or logical operations on one or more input busses. A symbol for

the ALU is shown in Figure 13-2.