16 Chapter Two
Introduction to Behavioral Modeling
The signal assignment statement is the most basic form of behavioral
modeling in VHDL. Following is an example:a <= b;This statement is read as follows: agets the value of b. The effect of
this statement is that the current value of signal bis assigned to signal
a. This statement is executed whenever signal bchanges value. Signal b
is in the sensitivity list of this statement. Whenever a signal in the sen-
sitivity list of a signal assignment statement changes value, the signal
assignment statement is executed. If the result of the execution is a new
value that is different from the current value of the signal, then an event
is scheduled for the target signal. If the result of the execution is the same
value, then no event is scheduled but a transaction is still generated
(transactions are discussed in Chapter 3, “Sequential Processing”). A trans-
action is always generated when a model is evaluated, but only signal
value changes cause events to be scheduled.
The next example shows how to introduce a nonzero delay value for the
assignment:a <= b after 10 ns;This statement is read as follows: agets the value of b when 10
nanoseconds of time have elapsed.
Both of the preceding statements are concurrent signal assignment state-
ments. Both statements are sensitive to changes in the value of signal b.
Whenever bchanges value, these statements execute and new values are
assigned to signal a.
Using a concurrent signal assignment statement, a simple AND gate
can be modeled, as follows:ENTITY and2 IS
PORT ( a, b : IN BIT;
PORT ( c : OUT BIT );
END and2;ARCHITECTURE and2_behav OF and2 IS
BEGIN
c <= a AND b AFTER 5 ns;